when the input to an inverter is low (0), the output is
the inverter output is the complement of the input
the output of an and gate with inputs a, b and c is 0 (low) when
the output of an or gate with inputs a, b and c is 0 (low) when
the and gate output is high only when all the inputs are low.
the or gate output is high when any of the inputs is high.
the nand gate output is low only when all the inputs are low.
the nor gate output is low when any of the inputs is high.
the exclusive-or gate output is high when the inputs are not the same.
the exclusive-nor gate output is low when the inputs are not the same.
according to the complexity classification, we can classfy ic into
when the input to an inverter is low (0), the output is
the output of an and gate with inputs a, b and c is 0 (low) when
the output of an or gate with inputs a, b and c is 0 (low) when
a pulse is applied to each input of a 2-input nand gate. one pulse goes high at t = 0 and goes back low at t = 1 ms. the other pulse goes high at t = 0.8 ms and goes back low at t = 3 ms. the output pulse can be described as follows:
a pulse is applied to each input of a 2-input nor gate. one pulse goes high at t = 0 and goes back low at t = 1 ms. the other pulse goes high at t = 0.8 ms and goes back low at t = 3 ms. the output pulse can be described as follows:
for a nor gate with 4 inputs, to get the output high, how many kinds of combinations are there in total?
which one is wrong in the follwing statement?
an inverter performs a not operation.
a not gate cannot have more than one input.
if any input to an or gate is zero, the output is zero.
if all inputs to an and gate are 1, the output is 0.
a nand gate can be considered as an and gate followed by a not gate.
a nor gate can be considered as an or gate followed by an inverter.
the output of an exclusive-or is 0 if the inputs are opposite.
two types of fixed-function logic integrated circuits are bipolar and nmos.
in fixed-function logic, the circuit cannot be altered.
dip is plug-in mounting
an and gate can have only two inputs.
a nand gate has an output that is opposite the output of an and gate.
for or gate, the output is high when any of the inputs is high.
an xor gate can have only two inputs.
the expression for a 4-input and gate can be x=abcd.
for a 2-input or gate, output x is high when either input a or input b is high.
the boolean addition 1 1=1 is right.
for a nand gate, when any of the inputs is low, the output will be high.
the boolean expression for the output of a 2-input nor gate can be written as .
soic package is much ller than dip.
the output is high when any of the inputs is high.
for 2-input or gate, the timing digaram is right.
the following timing diagram shows a xor gate.
the timing diagram below is a nor gate.
not gate also can be written as
typical ic gate packages are dip and
a&1=
for an nand with 3 inputs, when all the inputs are 1, the output is
continuously do the xor operation with 199 logic 1, the output is
if all the 3 inputs of a basic logic gate are 0, the output is 1, it should be gate.
clearly present the topic of the research paper you plan to write and publish the next. although you are encouraged to write the report in english, chinese presentation is also accepted at this stage. the topic report form can be downloaded from the week-1 courseware folder.
length of the draft (in 750 words) your working title and keywords introduction material & methods results & discussion (optional) references
this final paper is supposed to the paper you have been working on through the semester. this is also a chance to review and apply what you have learnt in practice. your score will be based on the paper's improvement inits structure and writing style. a = 45~50; b = 40~44; c = 35~39; d = 30~34